SerialSage

Flagship

Deterministic UART communication stack, FreeRTOS priority scheduler, and dual watchdog framework

C++

PSoC 5LP

Linux termios epoll

epoll

CRC-16

FreeRTOS

Unity Test

Baud Rate Range

9600 - 115200 bps

Host Latency

< 1ms Protocol Parsing

Memory Footprint

~4KB MCU • ~50MB Host

UART Frame Structure (Interactive)

CLICK BYTES TO INSPECT

START (0x7E) Frame Synchronization Delimiter

1 Byte

Marks the beginning of an incoming packet. When received, the state machine resets the frame buffer and begins payload accumulation.

Byte-Stuffing Rule: If 0x7E appears in payload or CRC, it is transmitted as 0x7C 0x5E.

SerialSage Core Layers

CLICK TO INSPECT PILLAR

UART Physical Layer

Configurable asynchronous serial driver with hardware flow control and termios integration.

Hardware I/O

Implementation Details

▸Supported baud rates: 9600 to 115200 bps with 8N1 framing.
▸Linux POSIX non-canonical mode with epoll event notification.
▸Hardware flow control (RTS/CTS) preventing microcontroller buffer overruns.

The Problem

Serial communication between embedded microcontrollers and Linux host computers is susceptible to frame misalignment, electrical noise, buffer overruns, and process stalls.

In industrial sensor nodes and robotics, a single dropped byte or blocked read call can stall the entire control loop. Standard raw serial reads lack framing boundaries, priority handling, and automatic error recovery.

Protocol Specification

SerialSage provides structured message transport between a Cypress PSoC 5LP microcontroller and a Linux host service. The communication layer implements a deterministic packet framing structure:

Field	Size	Value / Range	Description
START	1 Byte	`0x7E`	Frame synchronization delimiter
LENGTH	1 Byte	`0x00 - 0xFF`	Length of unescaped payload in bytes (0 - 255)
CMD_ID	1 Byte	`0x01 - 0xFE`	Target command identifier or response code
PAYLOAD	Variable	0 - 255 Bytes	Byte-stuffed application data
CRC-16	2 Bytes	`0x0000 - 0xFFFF`	CRC-CCITT polynomial `0x1021`, init `0xFFFF`
END	1 Byte	`0x7D`	Frame termination delimiter

Byte-stuffing and synchronization

Packets begin with 0x7E and terminate with 0x7D. If these control bytes appear inside the payload or CRC fields, the transmitter escapes them using 0x7C, XORing the original byte with 0x20.

Data integrity verification

Every packet includes a 16-bit CRC-CCITT checksum calculated over the length, command ID, and raw payload. Table-driven lookups on Linux minimize CPU usage, while cycle-optimized bit shifts run on the PSoC microcontroller. If the receiver computes a mismatched CRC, it discards the frame and transmits a negative acknowledgment (NACK).

Host and Firmware Architecture

Multi-priority queue system

Commands are routed through a thread-safe four-tier message queue using mutex locks and condition variables:

Critical: Emergency stops, watchdog heartbeats, safety triggers (preemptive dispatch).
High: Real-time sensor readings and motor position feedback.
Normal: Configuration updates and status polls.
Low: Debug logs and background telemetry.

The queue scheduler dispatches critical packets first, preventing low-priority telemetry from starving real-time control commands.

Dual-layer watchdog framework

System availability is guaranteed through dual watchdogs:

Hardware Watchdog (PSoC5): The MCU firmware configures a hardware timer that triggers a full hardware reset if the main RTOS control task fails to kick the timer within 500ms.
Software Watchdog (Linux): The host daemon expects periodic heartbeat frames every 250ms. If the microcontroller misses three consecutive heartbeat intervals, the host issues a hardware reset via GPIO and re-establishes serial synchronization.

Linux POSIX implementation & ncurses monitor

The host driver utilizes Linux termios for non-canonical raw serial configuration and epoll for event-driven asynchronous I/O (zero busy-waiting loops). An interactive 4-panel ncurses terminal displays live packet streams, service health, and throughput analytics in real time.